Copper has become the metal of choice over aluminum in the fabrication of integrated circuits because it has a lower resistance than aluminum and allows for the scaling down of devices. Despite its advantages, the use of copper in interconnect structures poses several special problems that did not exist with the use of aluminum. One such problem is the formation of copper hillocks. Copper is a soft metal and has a much higher expansion coefficient than aluminum, so that when it is heated under typical temperatures used in semiconductor processing it will expand significantly. Copper hillocks are a result of this expansion. Copper interconnect lines are typically formed by a dual damascene, or inlaid, metal process where both trenches and vias are etched into a dielectric layer and are then filled with copper metal. A barrier layer to prevent the migration of copper is typically formed in the trenches and vias before the copper is added. The copper within the trenches and vias is constrained on three sides by the barrier layer within the trench, and when heated it can only expand upwards or along the copper line. The copper expands from the copper line in the form of spike-like projections, hence the name “hillocks.” Copper hillocks are a serious problem because they can cause shorts and voids in dual damascene structures and MIM (metal-insulator-metal) capacitors, and can ultimately cause the early breakdown of the semiconductor device.
FIG. 1a illustrates a planarized copper dual damascene structure fabricated by a well-known technique. The dual damascene structure 1a has a first copper line 110 that is formed within a barrier layer 115 that is formed within a trench that was etched in a first dielectric layer 120. Copper hillocks such as 125 typically begin to form before any subsequent processing due to pent up thermal expansion energy in the copper. FIG. 1b illustrates the first interconnect structure 130 after a second dielectric 135 (typically SiN), that will serve as an etch stop layer, has been formed over the first copper line 110. The second dielectric 135 typically has a thickness 140 of between 650 Å and 1250 Å. A silicon nitride deposition is typically performed at 400° C., a temperature at which copper will expand significantly and form copper hillocks. The copper hillocks 125 that already existed before the silicon nitride deposition will grow larger, and additional copper hillocks such as 145, will form during the deposition.
FIG 1c illustrates FIG. 1b after a second interconnect structure 150 has been formed over the second dielectric 135 of the first interconnect structure 130. The heat and pressure exerted on the first interconnect structure 130 during the formation of the third dielectric layer 155, and subsequent layers, can cause the copper hillocks to grow even larger. The third dielectric 155 is typically carbon or fluorine doped silicon oxide that is deposited at temperatures of around 450° C. to 480° C. These temperatures will cause significant expansion of the copper and growth of hillocks. The growth of the large copper hillocks can cause a short 160 between the first copper line 110 and the second copper line 165. Also, the formation of hillocks can cause a void 170 to form within the first copper line 110.
FIG. 2 illustrates a simplified MIM capacitor 200 that has been formed by the conventional process of forming MIM capacitors. The bottom electrode 210 is typically formed by the conventional dual damascene process used to form copper interconnect lines. The insulator 220 is typically SiN and is deposited by PECVD at 400° C. The tantalum or TaN top electrode 230 is then deposited by sputtering or CVD. During the process of forming the MIM capacitor, copper hillocks such as 240 will form because of the heat and pressure exerted on the copper bottom electrode 210 during the PECVD deposition of the SiN insulator 220 and during the formation of an interconnect structure on top of the MIM. Some copper hillocks may grow large enough to cause a short 250.
Others have tried to solve the problem of copper hillocks in several ways. One solution is to use a thicker interlayer dielectric (ILD) so that the hillocks have to grow very tall in order to cause a short in a device. A thicker ILD will also help constrain the growth of hillocks because the hillocks will have to expend more energy to push through more material. The thickness of the ILD therefore has the effect of modulating the growth of the hillocks. But, increasing the thickness of the ILD is disadvantageous for the scaling down of devices and for devices such as metal-insulator-metal capacitors, where the thinnest possible dielectric layer is desired as the insulator.
Another solution to prevent the formation of copper hillocks is to reduce the temperatures used in the processing. Copper hillocks typically form at temperatures above 150° C. Therefore the reduction of the thermal budget of the processing can be restricted to temperatures below 150° C. Even the reduction of the thermal budget to around 350° C. can reduce the number of Cu hillocks defects. This is not effective in producing optimal semiconductor devices because such low temperatures produce materials having the undesirable qualities of lower density and less homogeneity.
Yet another solution to prevent the formation of copper hillocks is to anneal the copper before the chemical mechanical polishing (CMP) of the copper. The intent of this anneal is to expend most of the thermal expansion energy of the copper into the formation of copper hillocks that can then be polished away during the CMP step. By expending most or all of the thermal expansion energy of the copper during this pre-CMP anneal, hillocks are less likely to form at a later point. A similar solution is to form two ILD layers over the copper where the purpose of the first ILD is to cause the formation of copper hillocks and exhaust most of the thermal expansion energy of the copper. The copper hillocks would then be polished away along with the first ILD before the formation of the second ILD. These are not the best solutions because they require extra process stages and also risk the formation of voids in the copper interconnect structure due to the hillock growth.